1st Rd:
basic logic design, basic verilog/systemverilog syntax, setup/hold, etc. I think the only thing may not be on the book is timing result analysis which showed a few timing report and asked which one may have a better chance to fix, though it's still very simple.

2nd Rd:
e.g. list FPGA elements. They are just so simple that you must have seen them in your daily work

Question

1st Rd:
basic logic design, basic verilog/systemverilog syntax, setup/hold, etc. I think the only thing may not be on the book is timing result analysis which showed a few timing report and asked which one may have a better chance to fix, though it's still very simple.

2nd Rd:
e.g. list FPGA elements. They are just so simple that you must have seen them in your daily work

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