Cadence Design Systems Analog IC Design Engineer interview questions

There were two rounds of interview. I was asked questions on the gain of simple topologies like a mosfet having a current source at the top and source resistance find gain at source and the drain if input is applied at gate. Then current mirror accuracy.Then we have cmos inverter etc.Second round was about OTA then how can you reduce psrr in a given topology.Then setup time of some digital circuit.This was followed by an hr round