In RC circuit , I was asked to draw the O/P graph for step impulse. Then adding one more capacitor in parallel of R. Asked the time constraint and O/P graph for step response.
Analog Design Engineer Interview Questions
789 analog design engineer interview questions shared by candidates
Basic introduction about yourself,basics of verilog,projects,circuit fundamentals
feedback analysis, biasing, class-a amplifier basics
Review of the CV
They asked questions mostly related to VLSI design and verilog vhdl
Few questions on the MOSFET operation including the DIBL effect, and how vt of a MOSFET is improved when technology is being scaled down. How would one increase the gate capacitance
What was the biggest difficulty during your master thesis? (I just graduated)
Can you draw a block diagram of a Sigma-Delta modulator?
How to reduce the noise without changing zero and pole location
No resume questions, only standard FAANG questions and an RC circuit
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