Use min 2 input NAND to build a 3 input NAND
Asic Design Engineer Interview Questions
811 asic design engineer interview questions shared by candidates
Will the CMOS NAND gate speed up by increasing VDD?
How would you make Clock dividers?
which metal layer used for power/clock
Personality is the most important thing.
How to make an AND gate with only XOR gates
I felt the most difficult question was about different metal layers and their properties
varies and based on JD
Write some verilog for a 3 to 1 arbiter, with a priority client and 2 clients in a round robin.
Knowledge on OOPs concept. encapsulation and polymorphism. Function overload or overriding - Virtual, and non virtual function . Given a transmission of send and recv of a signal from 1 to 15 timeslots, find latency of signal from send to recv and determine and min and max latency . Probably looking for knowledge in counter and loops and logical thinking in the short span
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