How can you reduce the delay of an inverter?
Asic Design Engineer Interview Questions
811 asic design engineer interview questions shared by candidates
What is salicide layer? How is it related to self-aligned gates?
explain the project I did and DSP, FIR, FFT question
Counters, Flipflops, Latches, 32:8 Bit converter, State machine design, VHDL - Process statement, seuential logic, combo logic implementation, Functional coverage, code coverage - which coverage is crtitcal for verification sign-off and why ? , Different coding styles for FSMs, DV Environment diagram and explanation of last project in last company,.
Explain to us your thesis work? Designing the system from Top to Bottom?
what is a asic design?
technical- counter, data types (enum, struct), blocking and non blocking assignments. Aptitude- mixture and allegation, ratio and proportion, distance and speed, percentage, population based question.
what is setup/hold time?
Tell me about yourself.
Regarding testbench in sv and uvm
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