Verilog code for shift register.
Asic Engineer Interview Questions
1,319 asic engineer interview questions shared by candidates
How to determine if a taped out chip failed hold/setup timing
They asked me to complete a complex Verilog design, including testbench covering all conceivable corner cases, and a PowerPoint about it. It was obviously impossible to complete in the time allowed, so clearly part of the interview is to find out who submits to slave labor without complaint. Details of the design question are protected by NDA.
Why do you want to work for SpaceX?
About the projects I worked on.
Experience in taping out ASIC from start to finish.
Debugging scenarios of latest project
define metastability and how to deal with it in our designs
What is Setup time and Hold Time? Verilog and C syntax related Questions. Questions of Digital Electronics
There where no unexpected questions. All the questions where moderate.
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