Current project architecture and role. SV and UVM related. SV constraint, coverage, assertions. UVM architecture and flow. Verification strategy related.
Design Verification Engineer Interview Questions
1,114 design verification engineer interview questions shared by candidates
What is the difference between Mealy and Moore machines?
Uvm phasing process, different phases in uvm
What will you do if you made a big mistake?
Most Qs is very basic calculation and concept
FSM, Projects, Frequency multiplier, Data types
Introduce myself and previous experience
Questions were like: 1. Make 4:1 mux using 2:1 mux 2. Make and gate using 2:1 mux 3. Difference between asynchronous and synchronous reset. All the questions were like this only.
write code which returns error if we got 10 packets within 10 seconds
DSP, OOPs Concepts, Basics CMOS based concepts
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