How does polymorphism work in practice in OOP? How is it implemented?
Design Verification Engineer Interview Questions
1,114 design verification engineer interview questions shared by candidates
Computer Architecture. OOPs. System Verilog and UVM. Graphics Architecture .
design an electrical circuit with switches, voltage source for a particular application- wasn't expecting one since my area of expertise is mostly digital
2 signals, both only toggle once. At the first rising edge, start testbench; At the second falling edge, stop testbench. How?
45 mins phone interview: task vs function associative arrays packed vs unpacked scoreboard structures `uvm_do sequencer structure coverage: code vs functional functional cov: module and collector number of automatic bins for an int code coverage metrics uvm_object vs uvm_component concurrent vs immediate assertions 5hrs interview: reg model in uvm adapter and predictor scoreboard structure how to use some of the phases exercise on how to verify a DUT that gets data from 2 sensors list of quick questions on systemverilog how to verify req ack interfaces, also which assertions how to verify in a mixed signal enviroment find errors in given code (like missing "virtual" in parent/child sequences, or missing "automatic" in for loop with fork join_none) optimized way to generate Fibonacci's sequence recursive function to generate a given sequence shortest path algorithm: given starting point and destination point in a 2D matrix, get the shortest path from one to the other, including some non valid coordinates what kind of functional coverage I have done, how I've done scoreboards, some other questions about CV experiences
In the first round, the interviewer described a memory model consisting of L3 cache and main memory and asked me how will I verify it.
Explain how an out-of-order processor works? How do you implement register renaming? Difference between an architectural and physical register file
UVM based questions and Assertions and constraints
1. What are the pros and cons of adding an extra stage in a CPU 2. Follow-up: How does adding a stage affect the setup time and hold time
FIFO implementation Coding problem Asked about project i did
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