Highly obscure CMOS circuit trick
Design Verification Interview Questions
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digital electronics
gate questions ece
About UVM phases and how I use them.
Is there any problems like jitter, setup failure ,... etc? How would you make a counter overcome this problem
Can you give us some further explanation about the internship you did this year.
Why do you want to apply in ADI?
How to derive circuit diagram for finite state machine.
NOC : one side we have 3 AHB masters, 1 APB master and other side 3 APB Slaves, 0x0000_0000 to 0x_1000_0000 1st APB SLAVE 0x_4000_0000 to 0x_8000_0000 2nd slave oxC000_0000 to 0xFFFF_FFFF 3rd slave In addition to above imagine AHB master number 3 and APB master will provide error response for address range oxC000_0000 to 0xFFFF_FFFF. Note AHB master number 1 and 2 can still access address range oxC000_0000 to 0xFFFF_FFFF. Write a top_tb for this design ? What are the coverpoints or bins you can write ? What is difference between functional coverage and code coverage? If functional coverage is there, why code coverage is required?
Verilog code for basic circuits
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