Questions related to projects mentioned on the resume, Constraint questions, Write the verilog code and testbench for the given system
Design Verification Interview Questions
1,114 design verification interview questions shared by candidates
Verilog based questions and project related questions
1.system Verilog, UVM, Coverage based questions
Explain pg gate sims, few upf concepts
Basic Truth tables for NAND, XNOR, and similar logic gates.
Asyn FIFO and UVM detail Like YOU HAVE TO CODING IT.
The first question was to make from mix the function f=(abc’)’. After this I was asked to build a 4 to 1 mux from 2to1 muxes. Then I was asked about registers and they wanted me to build a FIFO.
Given Axi related specification and asked me to ask the questions related to specification.
SV, UVM, Driver sequencer handshake mechanism
1. They asked me to explain a flip flop function with wave forms and an rtl programme in Verilog. 2. I was given a sequence of input waveform and was asked to design a state diagram and also to write an rtl code in Verilog 3. Functionalities of the Universal gates, clocking domains, STA, few analogue questions 4. To explain the previously done projects of my academic qualification in detail
Viewing 291 - 300 interview questions