They asked me about uvm
Design Verification Interview Questions
1,114 design verification interview questions shared by candidates
apptiude was about the quantative, digital and a simple program. digital question are also simple you can search on internet. programming are also questions.
Debugging scenarios of latest project
About uvm Sv Ethernet Pcie Amba
What is Setup time and Hold Time? Verilog and C syntax related Questions. Questions of Digital Electronics
Call uvm_agent function from uvm_sequence to display "hello world"
1) Write the full adder code and testbench in Verilog? 2) Truth table of JK and D flip flop? 3) Why do glitches occur, and how to solve them? 4) Implement NAND gate using mux?
Questions on FSM, STA, FPGA, Verilog Basics, SV Basics,
Virtual interface, Functional coverage, TB
Amba protocols related Constraint for even and odd with modulo operator
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