Self intro Input file Floorplan Guidelines to macro Physical cells Taps cells Latchup effect Placement Output reports of placement What is setup and hold How to overcome setup violations
Physical Design Engineer Interview Questions
711 physical design engineer interview questions shared by candidates
Question related to previous project regarding how many issue you faced
Tell any 5 commands and how to validate floorplan
What is setup and hold time? How to fix any timing violation? Explain the sanity checks for each stage of the PD flow? What is crosstalk, EM, antenna violation?
Questions on our approach in solving the written test was asked.
How much experience in working on Block Level P&R. Describe Why Routing Required?
Mainly focus on deep concept of physical design like IR drop , Floating nets, Setup hold , pulse width violation ..
> Basics of PnR flow issues w.r.to congestion, cts, placement. > Any issues which faced in your previous project , how did you fix that ? > You should know about everything you write in the resume.
Basic of digital ,CMOS ,PD flow, CMOS power ,STA
You need to have a standard cell library to design your adder. What kind of cells you need and how many levels in each cell?
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