STA analysis for Flip-flops, basics of digital electronics and PD flows
Physical Design Engineer Interview Questions
711 physical design engineer interview questions shared by candidates
-> Questions on my projects listed on my resume. -> Questions on device parameters like short channel effects, temperature inversion, DIBL, Body Effect etc. -> Basic questions on PD Flow like files required for synthesis, P&R. -> Questions on scan testing. Stuck at faults. -> Few tricky questions on circuit implementation using Flipflops. CPPR, SI (especially crosstalk)
Draw 2x1 MUX using NAND gate and CMOS technology. Draw the same using AOI cell. How does Crosstalk affect the circuits?
Why NMOS is a weak transfer of 1 and string transfer of 0. What is threshold voltage and on what factors does it depends? What is IR drop? How is Leakage current related to temperature? Draw NOR gate using CMOS. What is Skew? Questions based on setup and hold time.
Text book hyperbole non practical theoretical questions. Does not test knowledge or how problem will be worked out with those questions which seems to be odd going by question types.
Question on power optimization technique beyond what the tools have options, basically looking for some innovative way of power optimization.
Coding to parse a netlist
It started from very basic introduction of yourself. 1. Overall experience , projects completed 2. PNR flow in detail and challenges faced in present company 3. Multicorner STA and power optimization 4. CMOS latch up
The process for lightning protection studies.
Whether setup & hold will come in same path?
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