Gave me a scenario and asked to develop a test plan to best verify the design.
Verification Interview Questions
3,807 verification interview questions shared by candidates
electronics and C, some measurement knowledge
When you run a simulation of 16ms, the simulation could take much longer (like 1hour) on a computer. Why?
6. programs in c, fsm design
They assessed only Computer Architecture knowledge. They asked about ARM architecture, Cache, assembly language, C language
What will be the last line of code in a UVM testcase?
Mostly technical
Find Largest Sum Contiguous Subarray
what are different type of FSM?
They ask about things mentioned in your resume, verilog, assembly language, RTL design etc.
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