DFT Engineer – Marvell

Location: Santa Clara, CA

Short Job Description

We are seeking a skilled DFT (Design for Test) Engineer with hands-on experience in Scan, ATPG, MBIST, Boundary Scan (JTAG/BSCAN), and Gate Level Simulation (GLS). The ideal candidate will contribute to DFT architecture, implementation, validation, and test coverage improvement for complex ASIC/SoC designs. This role offers the opportunity to grow into end-to-end DFT ownership across advanced semiconductor products.

Responsibilities

• Perform Scan insertion and Scan chain validation.
• Develop and execute ATPG patterns for manufacturing test.
• Implement and verify MBIST solutions.
• Design and integrate Boundary Scan (JTAG/BSCAN) architecture.
• Execute Gate-Level Simulations (GLS) including timing and non-timing verification.
• Support chip-level DFT integration and architecture development.
• Debug DFT-related failures and improve fault coverage.
• Collaborate with Design, Verification, Physical Design, and Test teams.

Required Skills

• Experience in at least two of the following:
• Scan
• ATPG
• MBIST
• Boundary Scan (JTAG/BSCAN)
• Gate-Level Simulation (GLS)
• Strong understanding of DFT methodologies and ASIC/SoC test flows.
• Experience with DFT implementation and validation.
• Debugging and test coverage optimization skills.
• Knowledge of semiconductor design and verification processes.

Preferred Skills

• End-to-end DFT ownership experience.
• Experience with large-scale ASIC/SoC designs.
• Familiarity with industry-standard DFT tools (Tessent, Synopsys DFT Compiler, TetraMAX, Modus, etc.).
• Knowledge of IJTAG, LBIST, EDT, Compression techniques.

Pay: $124,641.12 - $140,105.42 per year

Experience:

• Boundary Scan (JTAG/BSCAN: 6 years (Required)
• Scan: 3 years (Required)
• MBIST: 5 years (Required)
• DFT implementation: 5 years (Required)

Work Location: On the road