For over four decades, Cirrus Logic has been propelled by the top engineers in mixed-signal processing. Our rockstar team thrives on solving complex challenges with innovative end-user solutions for the world's top consumer brands. Cirrus Logic is also known for its award-winning culture, which was built on a foundation of inclusion and fairness, meaningful community engagement, and delivering enjoyable employee experiences at every turn. But we couldn’t do it without our extraordinary workforce – and that’s where you come in. Join our team and help us continue to make Cirrus Logic an exceptional place to grow your career!

We are seeking a creative and hardworking engineering intern to join our outstanding Analog/Mixed-Signal Verification, Modeling and Methodology Team. You will collaborate with systems and design teams to facilitate tops down design methodology through the development and validation of System Verilog (SV) models. You will also work with chip and DV leads to plan, setup, & execute AMS/UVM verification. Additionally, we are seeking innovative individuals who are interested in this position which will play a vital role streamlining development methodology for our organization. We are proud of our exceptional environment and multi-faceted culture. Join us and be part of our journey, innovating incredible technology on a global basis!

As an intern, you’ll collaborate with experienced engineers to solve real-world challenges, contribute to product development, and gain hands-on experience in a fast-paced, supportive environment. This internship will take place during the Fall 2026 semester over the course of a 12-14 week long internship working a full-time schedule.

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