Phone interview went on for 2 hrs. The manager was interested in my background and projects. Got an onsite interview call in 2 days. I had 6 rounds in the onsite interview, concentrating mainly on digital circuit design. Two of those rounds were implementation design, concentrating on RTL.
The questions were mostly from basics of circuit design. They tested timing, which is an important thing to prepare. FSM based design was tested.
Interview questions [1]
Question 1
Timing questions like critical path, setup and hold violations and ways to prevent them, dynamic logic and problems with timing there etc.
I applied online. The process took 2 weeks. I interviewed at AMD (London, England) in Jan 2026
Interview
1. HR call - slary expectation, relocation, general q/a
2. CV based interview with hiring manager (focusing on past relative work experinence)
3. 4 Tech interviews (problem solving, algorithms, job specific tech skills)
Interview questions [1]
Question 1
propose a design of the module based on provided specifications
It was smooth, i had three rounds with first being the screening. It was for internship so they mostly focused on intermediate level C++ programming for performance architecture role. It was a video interview via teams.
Telephone and video call,
Basics to projects
Resume based
Power sta front end
Back end
Synthesis
Vlsi
What are the challenge you will see in lower technology?
What are the inputs and outputs from the power analysis?
What are the checks after power planning is completed?
What are the power dissipation components? How to reduce them
Why float outputs are ignored but not float gates?
How do you calculate the core ring width?
What is IR drop? And how will you decrease this?
Interview questions [1]
Question 1
What are the challenge you will see in lower technology?
What are the inputs and outputs from the power analysis?
What are the checks after power planning is completed?
What are the power dissipation components? How to reduce them
Why float outputs are ignored but not float gates?
How do you calculate the core ring width?
What is IR drop? And how will you decrease this?
