Arm Principal Design Engineer interview questions

Very disappointing process. Initially position was advertised in Germany but then changed to Budapest. It felt like there was already pre-selected candidate for the position. I was given to write UVM verification plan for AHB-slave to SRAM. Assignment was sent to me 5:50pm Friday so there was no-one to clarify. I completed it anyway making RTL code with transaction level model for verification (not UVM though). But on the actual interview I asked about home assignment but was told it was sent to me by mistake. The interview questions were random. I observed complete lack of enthusiasm from the interviewers. We haven't discussed things like transaction level models, flow control and microarchitecture, although I tried to spark this conversation. I was refused without adequate feedback provided.