BAE Systems USA SystemVerilog/UVM FPGA Verification Engineer interview questions
based on 1 rating - Updated Jan 11, 2018
Averageinterview difficulty
Very negativeinterview experience
How others got an interview
100%
Applied online
Applied online
Interview search
1 interviews
BAE Systems USA interviews FAQs
Common stages of the interview process at BAE Systems USA as a SystemVerilog/UVM FPGA Verification Engineer according to 1 Glassdoor interviews include:
Phone interview: 100%
Here are the most commonly searched roles for interview reports -
I applied online. I interviewed at BAE Systems USA (Nashua, NH) in Nov 2017
Interview
A recruiter emailed me to schedule a phone interview. The phone interview was with the manager of the engineering team I would be joining and another engineer in the department. It lasted 25 minutes out of the 1 hour allotted time. The team manager was mostly the one talking and asking questions. I could tell the manager wasnt really interested in me. They never called me back after that. I was sent an automated email that I wasnt selected.
Interview questions [7]
Question 1
What would your past team members say your strengths/weakness are?