Marvell Technology ASIC Design Engineer interview questions

explain about cache

1st Round : Talked about RAW,WAW and WAR hazards and how is it solved/handled in both linear and OoO pipelines. Structural hazards caused and handled in OoO pipelines. 2nd Round: Was interviewed by 5 interviewers (45 minutes with each). Focussed entirely on my resume. Asked in depth questions on Tomasulo out of Order Implementation and Multi Clock Domain Fifo Design. Some of the questions were on Sequence Detectors, Simple Verilog design questions, Frequency Dividers and circuitry design. One of the interviewers gave a scenario and asked to wite a code to validate the integrity of the circuit (to test our VERIFICATION thinking ).