Marvell Technology Design Verification Engineer interview questions

Initial phone screen (2) by hiring manager + junior employee (<3 years out of college). Manager asks conceptual and higher level questions. Junior employee asks coding questions (dictates a piece of code and asks questions on that (SystemVerilog) Have to fill out online profile and NDA before going onsite. Onsite interview start with meeting HR person who collects compensation information and asks questions like why you left each of your previous employers, why you are applying now, what other companies you are talking to, what factors you will use to decide the offer etc. Later met with hiring manager (heads design+verif), 1 design engineer and 2 verif engineers (junior+senior). Hiring Manager asks high level questions: e.g where will you place coverage collection for stimulus applied to DUT (monitor Vs driver) Junior verif person asks more coding questions and Behavioural interview (how to deal w/ diffcult person, failures in past etc) Design engineer asks some Verilog question and how to test a particular design. I give all of them an A for the interview. Other Sr Verif engineer was extremely challenged even to speak couple of sentences in English. He just thrust a piece of paper in front of me typed with a couple of questions. They had non standard terminology and despite repeated requests to explain the terms refused to do so. He kept repeating "just read the question and answer it". After some time I figured out what was the question and gave the answer. He claimed the answer was wrong and asked me to try again. After I came back I googled and found that my answer was correct. He could have moved on to additional questions and had a better/larger sample to make a decision, but stuck with the 2 questions throughout the 45 minute interview. This person should have been trained and lacked basic communication/interview skills in English. Be prepared for coding questions (some code w/ bug in it etc) regardless of how experienced you are.