Synopsys Application Engineer I interview questions

I was asked questions on Verilog/VHDL basics, Testbench concepts, RTL coding, FSM models. system verilog assertions etc. questions related to past work and VLSI flow. Digital design concepts like adders, fsm, logic optimizations.

I apply for the role in Japan and have interview with people in Japan site before. But I got rejection. Then HR suggest me to put my resume back to Taiwanese pool and I get another chance for interview. phone call -> technical interview -> senior manger interview ->HR -> offer get