I applied online. I interviewed at Synopsys (Bengaluru) in Sep 2024
Interview
The interview process consisted of three rounds — a written technical test, a design verification technical interview, and an HR discussion. Questions mainly focused on Verilog, SystemVerilog, UVM concepts, and project experience. The interviewers were professional and emphasized practical understanding and debugging skills.
Interview questions [1]
Question 1
What is the difference between blocking and non-blocking assignments in Verilog?