Verification Design Engineer applicants have rated the interview process at UST with 2.7 out of 5 (where 5 is the highest level of difficulty) and assessed their interview experience as 67% positive. To compare, the company-average is 64.9% positive. This is according to Glassdoor user ratings.
Candidates applying for Verification Design Engineer roles take an average of 8 days to get hired, when considering 3 user submitted interviews for this role. To compare, the hiring process at UST overall takes an average of 17 days.
Common stages of the interview process at UST as a Verification Design Engineer according to 3 Glassdoor interviews include:
Presentation: 40%
One on one interview: 20%
Phone interview: 20%
Drug test: 20%
Here are the most commonly searched roles for interview reports -
The interviewer is friendly and willing to listen patiently. The process is around 30 mins with technical questions and questions about final year project. The interview is conducted through online.
Interview questions [1]
Question 1
What's the different between CPU and microcontroller
Interview comprises of either one or two rounds,
Mostly online interview, either telephonic interview or Zoom (or Microsoft Teams or Google meet) call.
Interview lasts for 20-40 minutes.
HR round is optional.
Interview questions [1]
Question 1
Basics of SV and UVM. Few more depending on your experience, based on you previous projects(if any).
I applied through a recruiter. The process took 1 day. I interviewed at UST (San Diego, CA) in Nov 2021
Interview
Recruiter + Hiring Manager in a Zoom call. Generally, since UST is based in India, early mornings or late evening interviews. Majority of questions are broad technical questions, no experience questions.
Interview questions [1]
Question 1
* Have you used UVM?
* What is your knowledge level of SystemVerilog?