Not much. A good preparation of electronics basics, verilog and C++ languages can easily get you through the test and interview.
Asic Design Engineer Interview Questions
811 asic design engineer interview questions shared by candidates
Questions 1st technical interview: Talk about yourself Talk about your project networks problem from question paper how does the power supply at home work between two to three rooms Flip flops timings questions frequency of 11 inverters in series detailed questioning of NMOS structure operations functioning secondary effects probe into channel length modulation CMOS inverter switching power there, static power and dynamic power formula logical puzzle:consider 2 taps (tap a and tap b) as inputs AND gate OR gate and XOR gate then take the same logic and build a water tank, locate the taps so that the functionality of the gates hold good Questions I got wrong in the question paper Resume-based questions
what are glitches. hoe to eliminate them
1st technical interview: Talk about yourself Talk about your project networks problem from question paper how does the power supply at home work between two to three rooms Flip flops timings questions frequency of 11 inverters in series detailed questioning of NMOS structure operations functioning secondary effects probe into channel length modulation CMOS inverter switching power there, static power and dynamic power formula logical puzzle:consider 2 taps (tap a and tap b) as inputs AND gate OR gate and XOR gate then take the same logic and build a water tank, locate the taps so that the functionality of the gates hold good Questions I got wrong in the question paper Resume-based questions 2nd technical interview: Out of the box thinking helps here project related question: gaussian distribution a lot of static timing analysis questions, tricky a D FF with clock input as an AND gate with inputs A and clk, now remove AND gate to give a clean clk but the functionality of the circuit should remain the same. talk about the kind of job they do, the kind of job I want to do, offers at hand, training details, date of joining details HR round: A talk about future aims of my life and culture at OS, the perks of being a small company, etc etc
assertion and deassertion of asynchronous reset signal, what's the effect on the system
if a signal backpressures the writing agent of a 8 deep fifo on cycle x and the writing agent stops 2 cycles later what is the logic to create a signal to backpressure the fifo.
Explain functioning of different types of memory cells.
Questions related to verilog, microcontrollers, digital electronics
in written test there was 40 Marks test which included aptitude, digital and analog electronics questions
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