A question they asked was to code a Full Adder in Vivado using the logic equations that you have to derive and then simulate it using a test bench.
Asic Design Engineer Interview Questions
811 asic design engineer interview questions shared by candidates
FSM Design
Async FIFO sizing. Thru put of putting every clock cycle. Both read and write clocks are same speed
The interviewer asked some verification questions - those were nice; but then he also asked a software (i.e "cracking the coding interview") type of question. I'm not a Software Engineer
2 input NAND gate, which states will have how much leakage power.
What is your background?
AI questions included about auto encoders, lstms, basics of neural network, convolutional neural networks etc.
Gate-level design, CDC questions
Focus was on physical design.
Questions on PCIe, CDC, Pipeline
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