Static timing analysis and Clock domain crossing
Asic Design Engineer Interview Questions
811 asic design engineer interview questions shared by candidates
Python question and verilog question to implement the same thing
introduce your last position/ project?
One of the questions is about clock divider and the interviewer asked a lot different questions related to divider design
basic concept of pipeline state machine of sequence detector C program of a function about pattern replace
Out of Order Processors, Standard Pipeline Description, Cache Memory Design, State Machine Design
Describe a time when you have to overcome a setback on a project.
What is your thesis work?
It consisted of 2 rounds. In Round 1 they asked about basics of digital electronics, cro, osciloscope. In Round 2, they asked to code traffic light controller o verilog and discuss its area, power
Draw the FSM of detecting a sequence pattern "1101"
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