Write RTL code for a fifo.
Asic Design Engineer Interview Questions
811 asic design engineer interview questions shared by candidates
pd flow and physical verification questions
CMOS, Digital Design, Analog basics, VLSI questions
The first thing was a phone call with the recruiter where he asked questions like my interests, past experience, graduation date, etc. In the coding round 1: SystemVerilog FSM question + behavioral Then the coding round 2: Python question + behavioral
no many hard questions. Based on resume.
Tell me abuot your self
They asked me to write the Verilog code for a D-Flip Flop. I had forgottend verilog, so I asked them if I could write it in pseudo-code. I dervied and wrote the code from first principles. I think this impressed them.
fifo deepth calculation using 1 32-bit adder to add two 64-bit data detect every value 1-bit position for a signal
Why do you want to work here?
Describe two ways to double throughput in this provided circuit.
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