Write a Fibonacci number generator in Verilog, output a number in each cycle.
Asic Design Engineer Interview Questions
811 asic design engineer interview questions shared by candidates
Digital Design basics
Tell us about interesting problems you uncounted and how you solved them
Two questions： 1. 2 2bits comparators to 4 bits comparators, and reduce the delay to 1 units 1. data buffer like 0100000001, most simple rtl design to get the length (which is 9)
design sensor with minimal logic block
explain about cache
The interview was straight forward and aveage
Explain the working of a FIFO.
Do you have any experience about FPGA?
Some code test. Some system knowledge test.
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