Verilog code for shift register.
Asic Design Engineer Interview Questions
810 asic design engineer interview questions shared by candidates
How to determine if a taped out chip failed hold/setup timing
They asked me to complete a complex Verilog design, including testbench covering all conceivable corner cases, and a PowerPoint about it. It was obviously impossible to complete in the time allowed, so clearly part of the interview is to find out who submits to slave labor without complaint. Details of the design question are protected by NDA.
Why do you want to work for SpaceX?
Experience in taping out ASIC from start to finish.
Debugging scenarios of latest project
What is Setup time and Hold Time? Verilog and C syntax related Questions. Questions of Digital Electronics
Call uvm_agent function from uvm_sequence to display "hello world"
They ask many things about your thought and knowledge.
first, some of engineer will ask a lot of question and you will give a presentation to introduce your project. After that, three person will ask your opinion about samsung, job.
Viewing 711 - 720 interview questions