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Asic Engineer Interview Questions
1,319 asic engineer interview questions shared by candidates
Question regarding Logic design, Verilog ,State Machine- pattern detection, Comp Arch- Pipeline, hazards, cache, associativity, Basic Perl were asked.
- Questions on different types of cache - Difference b/w them - Explain inclusive and exclusive caches
This was the main interview question. Design subroutine (pseduo code) that takes variable length of array whose element are in consecutive order but has one missing element. And minimum length of array should be 2. First and Last element can't be missing
Possible solution vectors to meet set up timing
FIFO design
How to implement not with nand/nor gates
muxs verilog
I can't say exactly but one SystemVerilog question was to implement a finite state machine given a certain output. Review sequence detectors.
Write the verilog code for a counter then change reset to asychronized.
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