1st round: asked basic verilog questions like difference between wires & regs, difference between if-statements and case statements. Asked about projects on resume. Asked a small project and how I should approach it. 2nd round: gave a problem and had to create FSM and verilog.
related to projects Verification environment
Emerging technologies in the microchip industry
Current project architecture and role. SV and UVM related. SV constraint, coverage, assertions. UVM architecture and flow. Verification strategy related.
What is MOSFET, EDA etc.
ok. fifo..design n implementation.and other designing questions
What is a fpga and what is a lookup table?
What is your Ph.D. research?
what are the sources of noise in image sensors? A/D types
Write a Fibonacci number generator in Verilog, output a number in each cycle.
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