cmos fundamentals, rtl design, verilog, physical design flow, static timing analysis and some aptitude questions
Asic Engineer Interview Questions
1,319 asic engineer interview questions shared by candidates
the uvm knowledge for register model
Using basic gates to build a full adder. Draw FSM and how to verify it using C. Also many C/C++ questions and computer architecture questions. And give you some clock diagram and ask what component will result in that diagram. Overall not very easy questions.
Describe a project where you have to regularly communicate with team members.
Brief explanation about projects done
if the input of an inverter is floating, what would the output be?
Whats inside a SRAM?
Setup hold time,
Everything was easy. Counter Design using Moore Machine, Counter Code in verilog, Clock Domain Crossing Questions and MCP in PT
Phone interview questions: 1. How do you achieve run time polymorphism? 2. What is meant by casting of objects?
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