Once written test qualified , they called for interview In the interview process, they were asking me to solve 10 verilog programming questions, 10 puzzles In technical interview questions are design of Mux, clock generations, 2s complement design , swapping of two numbers using blocking and non blocking , parity checker design. one questions is , given the RTL code for that design the net-list circuit
what are the impacts of using very tight skew constraints
Why are you leaving your previous organization
What is setup and hold?
How to synchronize a clock in two different time domain? Hold/setup time violation and how to fix? Questions from timing analysis
I was asked to describe the projects I had done related to VHDL, ASIC design etc. After that I was questioned about debugging the RTL code.
Questions mostly related to semiconductor processes and techniques
how PTV affects performance
diff between false path and multi cycle path
Tell about Your self and some other related questions.
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