how to solve clock skew, detailed process
Asic Engineer Interview Questions
1,319 asic engineer interview questions shared by candidates
how to find if an a number is unassigned in an array?
Standard design questions.
how do you know you have cover all the case in your testbench
Coverage analysis, STA, DFT, Write verilog code for counter, differet way to give delay in verilog code.
questions on digital electronics and verilog
* A lot of computer architecture questions. * Some simple Verilog questions. * Few software related C/C++, compiler, perl scripting questions. * No behavioral/HR question at all.
1st Round : Talked about RAW,WAW and WAR hazards and how is it solved/handled in both linear and OoO pipelines. Structural hazards caused and handled in OoO pipelines. 2nd Round: Was interviewed by 5 interviewers (45 minutes with each). Focussed entirely on my resume. Asked in depth questions on Tomasulo out of Order Implementation and Multi Clock Domain Fifo Design. Some of the questions were on Sequence Detectors, Simple Verilog design questions, Frequency Dividers and circuitry design. One of the interviewers gave a scenario and asked to wite a code to validate the integrity of the circuit (to test our VERIFICATION thinking ).
mentioned above
loop stability calculation, dominant pole
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