In my question paper they were asking the .. 1. comp of SRAM and DRAM 2. si bandgap 3. design circuit using NAND gates 4. function and task in verilog 5. verilog programming 6. static timing analysis 7. k maps 8. self compliment codes 9. related to network analysis
Design guidelines and concepts; the earliest available on board time.
How to solve CDC problems
I had all my questions related to my job.
What are RTL, Gate, Metal and FIB fixes?
How does a JTAG probe work
About the things in Resume
What is setup time/ hold time violation ? How are they related to the frequency.
Array, system verilog,uvm, mailbox Queue fifo configdb etc
Explaining the concepts of setup time and hold time in digital chip design
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