Tell us about your interests. Do you prefer digital or analog and why? What class of transistors did you use for your project?
Circuit Design Engineer Interview Questions
154 circuit design engineer interview questions shared by candidates
Hold,setup,metastability,jitter,types of jitter, what causes each of these., and other clk questions: A dive into certain aspects of circuit/clk design.
Timing and power optimization for low power.
Draw a transistor level latch and D-FF.
nMOS gate capacitor VS gate voltage
What is Hold time ?
Details of setup and hold time, basic digital design questions on mux and different flip-flops, transistor sizing, leakage control, Verilog coding etc.
Setup and hold time, Leakage and dynamic power, sizing of transistors in combinational gates
1. Digital custom design - setup/hold constraints, clock skews, crosstalks, layout related clock routing queries, wire delay.
FIFO setup/hold time state machine
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