Calculation of fifo depth for buffer from cpu to memory
Cpu Verification Engineer Interview Questions
83 cpu verification engineer interview questions shared by candidates
Most Qs is very basic calculation and concept
C, VHDL, Verilog. Microelectronics, computer architecture
C programming
find the depth of a tree in c++
computer architectures and operatives systems
32Kb cache, 2 way assoc. and 64B line. what is the cache state and line state according to MESI when. Read 0x010F30 then write 0x880F00 then write 0x010F20
Lot about past experience and projects, Arbiter design, OOPS concepts, scripting, verilog, Asynchronous/synchronous FIFO, Computer Architecture, Verification concepts. However most of it was focussed on prior experience.
Basic Computer Architecture questions. How to extend a 5 stage pipeline to 6 stages. Effects of doing that etc. A few programming questions.
Pipelining, latency and throughput, Cache, types of cache, problem on set way associative cache, interrupts, Virtual memory, page fault, project.
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