Synthesis constraints Timing checks - setup, hold Related discussion - setup from one FF (in fast clk) to next FF (in sync fast clk/2) Hold for the above scenario Clock Gating How to write RTL assertions
Design De Ic Interview Questions
402 design de ic interview questions shared by candidates
Explain your resume, explain your research, where do you see yourself in 5 yrs
What is the gain and bandwidth of the given circuit?
Technical question mostly about the digital things. They asked to draw schematic diagram of Inverter using transistor level. Stick diagram . Also draw XOR gate by only using nand gate.
Timing analysis on a given digital circuit. How to pipeline the given design.
Same question as shown by others, find Voltage at S when D is fixed at different G voltages but did not make clear if S was grounded. Later said S is not grounded and then interviewer got pissed as asking further questions about the problem and hung up the phone.
How start up circuits of a bandgap works?
Questions about electronics or electronic circuitry
Explain about basic op-amp and then explain the gm/id technique used to design. Miller compensation technique and the compensation mechanisms and basic single-stage amplifier.
Asked for the IC backend design flow and education exp in IC design. Also asked about blockbuild and meeting timing expectation. What are the IC design tool exp
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