7 questions total. One about arm products, 2 about coding in any programming language you want and 2 about coding in VHDL. Last question was if I Had any questions.
Design Verification Engineer Interview Questions
1,113 design verification engineer interview questions shared by candidates
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Draw a block diagram of a simple processor and explain how a particular instruction will flow through it.
Assertions,SV OOPS, Comp Arch
return count of characters in a string, in C
How to design an Accumulator. How to generate ramp signal in verilog. What are start and stop bits. Min. delay and Max. delay.
What is ASIC Design flow?
Digital Electronics:- FSM, Register, Flip flop, MUX. Verilog:- write program for FSM, clock generator, mux. SystemVerilog:- programming question based on randomisation. UVM:- write code for driver sequencer ,Tlm ports.
Write some code to efficiently sort three input number from hardware perspective
Describe your last working experience.
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