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Design Verification Engineer Interview Questions
1,113 design verification engineer interview questions shared by candidates
1. Difference between Temperal and Spatial 2. Difference between Shared Memory and Memory Passing 3. How to transfer a float number to integer in c++ 4. questions about class, inheritance, polymorphism and so on.
How would you verify a write-back 4-way set associative cache using assembly language programming.
expected salary with respect to your experience
What are the components used in an additional circuit?
Identify stress concentrations on a PCB
Interesting question about memory aliasing. You've two APIs write(addr, data) and read(addr, &data) just using these two APIs write an algorithm to identify one of the internal signals that has been shorted. You've no access to internal signals or the interface signals (black box verification)
Linked List traversal, Fibonacci algorithm (basic and recursive), the difference in complexity between the basic and recursive. Relatively straight forward. Second phone screen: "A person on a stairway needs to get from the bottom of the stairs to the top in the minimum number of steps, no, how possible combinations of steps, no, I don't think I explained that well...what if they took could only take one step forward for every"...really? is this even a real question? somehow the answer was yet again a Fibonacci sequence question. Next was reversing a singly linked list - oops, you can't use any references (!?), or another linked list.. Frustrating to have gotten the "B" team interviewer
Do you think your team spent too much time for the (simple) design you worked on (with a smile that hints that my team doesn't know what we are working on)?
Jk flip flop,logic gates,register table (embedded) k map and some VLSI basics
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