First it was a skype interview after resume shortlist. Second it was in the company itself where there was a written exam consisting of digital, analog, apti and C. Followed by project related interview and some design related question(frequency converter).
differenece between function and task , equality and case equality operator, wire and reg and logic, case and casex and casez, dynamic array and queue, what is mail box
Core Digital Perl, C and UVM Given to solve may circuit problems How to code xor gate with multiplexers.
Draw a count to 5 counter logic circuit.
Given variable vector should be randomised as unique values but without using a system verilog keyword which is generally used
Explain different phases in the UVM and their importance?
Topics like pipelining & hazards, Cache, Assembly language, VHDL, C, frequncy divider, clock gneration using VHDL are touched in the technical rounds. And a question to explain my project from digital design is asked.
digital electronics and verilog
How would you debug a failing simulation where coverage is not met?
Basic question in SV, UVM, Verilog, Linux
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