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Design Verification Engineer Interview Questions

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1,114 design verification engineer interview questions shared by candidates

Basic digital, verilog questionscan be answered if you know the concepts well, Sv was totally into randomization , coverage and assertions. Uvm basic things initial rounds and in depth in last round. In manager round all digital, verilog, sv and uvm were covered
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Design Verification Engineer

Interviewed at Micron Technology

3.9★
Dec 19, 2020

Basic digital, verilog questionscan be answered if you know the concepts well, Sv was totally into randomization , coverage and assertions. Uvm basic things initial rounds and in depth in last round. In manager round all digital, verilog, sv and uvm were covered

There's a circuit diagram of a pulse generator: a 2-input NAND gate with one of the inputs three inverters downstream from the other input, with some propagation delay for each inverter. Given the timing diagram of the input, what does the output look like?
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Design Verification Engineer

Interviewed at Micron Technology

3.9★
Aug 25, 2021

There's a circuit diagram of a pulse generator: a 2-input NAND gate with one of the inputs three inverters downstream from the other input, with some propagation delay for each inverter. Given the timing diagram of the input, what does the output look like?

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