Q: SystemVerilog syntax questions Q: Design a clock in verilog without any existing clock signals Q: Some flip-flop/latch design questions at clock-domain crossing.
Design Verification Engineer Interview Questions
1,114 design verification engineer interview questions shared by candidates
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Questions on Digital electronics, CMOS, Physical Design and LVS
Code C++ - to print Fibonacci series using C++
About system verilog , verilog, digital electronics
1)data should be <20, this was the constraint existed, but you should make the data in range 30 to 40 without using constraint_mode. 2) what the uses of bins in coverage
CDC, HW design, testbench engineering, etc..
Implement a circuit board the receives an 8-bit bus. The output is an 8-bit bus where the first net that is '1' in the input is also '1' in the output, the rest are '0' (in other words - "find first '1' in the input bus).
General questions in Python, C, Verilog, and SystemVerilog.
How to use muxes to implement an XOR gate?
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