How will you deal with a difficult design engineer?
Design Verification Engineer Interview Questions
1,114 design verification engineer interview questions shared by candidates
Verilog Design and verification related
Are you familiar with System Verilog
Questions related to pipelining, hazards, in-order processor, out of order processor, Register renaming, branch prediction, caches and virtual memory
Teamwork that related to the position.
UVM concepts, assertions, tb arch
What's pipelining? What's cache coherency?
My previous experience, basic assertions and fifo programming
Lcm, Swap, Factorial for C coding Write constraints in system verilog
What products of the company do you know? tell me a project you have done in the past and what did you learn form it..what would you change.. write 2 little projects in VHDL or Verilog (a state machine and a counter).. explain what you did..
Viewing 501 - 510 interview questions