Computer Architecture, Logic design, validation, software, behavioral.
Design Verification Engineer Interview Questions
1,114 design verification engineer interview questions shared by candidates
functional coverage, types of bins, types of array, constraint examples, virtual class,threads
consider a transaction between two components (data -8 bits and address- 32 bit) .Mismatch happens between expected and received data , What are the expected issues ?
Digital Logic, Computer Architecture, SystemVerilog, UVM, basic PERl
Questions about debug of failure
Design a bitstream pattern detection finite state machine in the HDL of your choice.
described in the interview process.
Scripting and programming interview was about file parsing and automation (Analyse the code, find the error, correct it) General keep an eye on digital design concepts like FSMs, Clock and Timing, CDC, etc.
Some standard programming questions, hardware and power specific design questions, as well as test philosophy.
Given a 32 bit signal, create a SystemVerilog constraint that ensures that only 2 bits are flipped in randomization.
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