Design a d latch using 2:1 MUX?
Design Verification Engineer Interview Questions
1,114 design verification engineer interview questions shared by candidates
What is the difference between latch and flipflop
Basic questions on digital like flip flop, latches ,verilog pattern detector code ,connection types,system verilog OOPs concepts ,arrays ,Basic questions on UVM like factory,common phases.
They asked About Projects initially and then core
Verilog Design based questions like: Difference between Mealy and Moore FSMs?
Should be clear with basics in System Verilog and UVM to clear the technical rounds. Interviewer mainly focus on projects and ask to implement uvm testbench components and explain the process
Do we run a sweatshop or do we play
Explain past job positions, what tasks you had to fulfill and how you did it.
Verilog all basic questions of digital
Setup time hold time
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