Difference between blocking and NB ,Delays, Mux, Encoders, Sequential design
Design Verification Engineer Interview Questions
1,114 design verification engineer interview questions shared by candidates
basics from sv, uvm, verilog
I was asked to give a brief on PCIe protocol
1. Write constraints for 32 bit variable,where for each randomization it should only flip any two of the it's bit's..
Discuss your research project as part of your self introduction
introduction? Digital combinational question? Sequential? verilog basics, operators,clock generation etc
some of the basic question from verilog and system verilog. questions from constraints and assertions. questions from STA. they will explain a model or a block you have to write the code for that
Why do you want to apply for this job
Verilog program for d flipflop
1. about asynchronous feedback logic. I did not know asynchronous circuits.
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