About APB protocol, basic digital and sv,UVM questions
Design Verification Engineer Interview Questions
1,114 design verification engineer interview questions shared by candidates
1. difference between flip flop and latch. 2. difference between blocking and non blocking. 3. System Verilog verification architecture. 4. difference between verilog and system verilog.
Two leetcode style questions on arrays, asked to find the output of a SV code and writing Driver class for an SPI with single master and multiple slave.
Q. Write assertion on a stated scenario Q. Questions on code and functional coverage
In round 1 - 19 MCQs related to general concepts, a mix of digital and analog electronics, mainly digital. 3 subjective question from - STA, STA, FIFO depth calculation 2 circuit design questions - FSM sequence generator , differently clock delayed output using MUX and flip flops. Round 2- Started with basic STA questions and went up to solving some on paper. Later digital design questions about mux , flip flop, counter, clock divider , FSM. Basic Verilog code like Fibonacci numbers generator , counter. MOS - MOS inverter questions and sub threshold region conduction. Short channel effects.
Describe the steps in an AXI transaction.
Q: Write me a factorial Q: Write me a script that fills in a set of parameters for automation specified by a user. Q: What is a fork? What is the difference between fork join_none and fork join_any? Q: Tell me more about the project you did in your Computer Architecture class?
they mainly concentrate on protocols knowledge and Verilog and constrains in SV
Interview consists of digital electronics,verilog,project based questions
What is the one thing that you are proud of yourself during the learning process ?
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