How to design a UVM testbench for a given design. What all componets are needed etc. Corner cases to test out and efficient way to build environment
Design Verification Engineer Interview Questions
1,114 design verification engineer interview questions shared by candidates
System Verilog Virtual functions
System Verilog ,UVM Basics, Questions on Resume. Assertions,Constraints. Memory Verification plan
Constraint for 8-bit opcode (SystemVerilog) ➤ Only one bit can be set in the 8-bit opcode (i.e., one-hot encoding). Matrix size based on opcode bit index ➤ Based on which bit is set in the 8-bit opcode, generate a square 2D array (e.g., if bit 4 is set, matrix is 4x4).
Constraint randomization based question linking to AXI and memory filling
Confidential. But related to system verilog and uvm.
Since the interview was for a hardware position, they asked more software related questions than I expected but were all easy
How do you increase processor speed.
Basic Pipeline questions focused mainly on Branch Prediction and BTB
design a vending machine from architecture to rtl..
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